![]() ![]() ![]() Given that I already suspect this one is unfair bc at the beginning, AES-XTS (also, what’s the key size? It matters alot!) benchmark in software (no accel crypto) just does not match up with my result (mine are +6M/s for 256bit key, +15M/s if 128, total 37M/s per core key, OpenSSL 1.1.1). It then ends up that you still get your rpi3 performance or A77 performance or M2 performance or whatever, you just didn’t read or understood spec and datasheets before you buy. I just don’t get the purpose of these benchmarks. JH7110 will do this task, sure, but my guess it’ll take four days of uptime (yes I tried). For example, it takes literally ages to build a Slackware-15.x huge.s kernel on my i7-8750H (about six to ten hours), and I have to say that it is much better CPU that what I had before (AMD Athlon64x2 4800+ from 2009), but it is already worse than I have in my Fairphone 4 (Snapdragon 750G, A77), by about factor of 1~2. You’ll quickly notice differences at least in compile times of typical Linux kernel configs. My guess guys, the “real workload” is it how you feel about it, give a time, get used to it and compare In fact, what is run is actually simulating the execution of the Reduceron functional machine, itself running a non-trivial Knuth-Bendix logic solver (inception all the way down).įYI, Verilator simulation is a Known Hard problem and I have inside knowledge that it is one what the key processor companies actually study and measure. ![]() There’s no "“1000 times a+b in 1 second” " in this workload. I don’t know what you hope to achieve with the last insult. (There are work on multi-threading for very large and very partionable RTL, but that’s problem specific - my test is single thread). This is a single-thread workload as the state is the input to the logic cloud and every cycle it’s different. RTL simulation, by their very essence tries to execute the logic expressed by the RTL for millions of cycles. And while in this case the Verilog input looks unusual, it doesn’t matter for the actual C code that Verilator produces. In my day job, I do run RTL simulations that take far longer than that. I’ve already explained that this is a typical, non-synthetic, example of a Real Workload. ![]()
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